1. Field of the Invention
The present invention relates to a semiconductor device of the LDD structure formed on an insulating substrate and a manufacturing method thereof.
2. Description of the Background Art
FIG. 12 and FIG. 13 are sectional views showing a method for manufacturing a conventional semiconductor device of the LDD structure.
As shown in FIG. 13, a silicon layer 3 is provided on a silicon substrate 1 with a buried oxide film 2 which is a silicon oxide film interposed therebetween. Such structure including the silicon substrate 1, the oxide film 2 and the silicon layer 3 is called an SOI substrate. This SOI substrate is manufactured by the SIMOX method by the oxygen ion implantation method, the wafer sticking method, etc. Part of the silicon layer 3 is removed or selectively oxidized so as to be electrically isolated from other elements.
A gate electrode 8 is provided on the silicon layer 3 with a gate insulating film 7, such as a thin oxide film of about 100 angstroms interposed therebetween. A channel formation region 4 for formation of a channel is provided in part of the silicon layer 3 under the gate electrode 8. Usually, the conductivity type of the channel formation region 4 is P-type in NMOS and it is N-type in PMOS, which is formed by introducing impurities of a conductivity type opposite to that of the source, drain portions, but which may be of the accumulation mode in which impurities of the same conductivity type as the source and drain are introduced, according to circumstances. The accumulation mode allows a low threshold voltage.
Sidewalls 9 are formed on the side wall of the gate electrode 8 above the channel formation region 4. An additional drain region 5 and an additional source region 5' are formed under the sidewalls 9, 9, and a drain region 6 and a source region 6' are formed adjacent to the additional drain region 5 and the additional source region 5', respectively.
In such a structure, if a certain gate voltage is applied to the gate electrode 8, carriers of the same conductivity type as the source, drain are caused in the channel formation region 4, and the amount the carriers changes depending on the applied gate voltage, and thus the MOS operation of controlling the current value with the gate voltage is obtained.
The additional drain region 5 and the additional source region 5' are used to moderate the drain electric field to enhance the operational breakdown voltage.
Actually, the drain region 6, the source region 6' and the gate electrode 8 are respectively connected to metal lines with low resistance, such as aluminum, for extension to enable connections with other transistors, and the like.
Next, a method of manufacturing this structure will be described.
As shown in FIG. 12, the silicon layer 3 is formed on the silicon substrate 1 with the buried oxide film 2 interposed therebetween to realize the SOI structure. Usually, such structure is formed by performing a high temperature heat treatment at about 1300.degree. C. after adding oxygen ions of about 0.4-2.0.times.10.sup.18 /cm.sup.2 into the silicon substrate 1. In the case of a dose of 0.4.times.10.sup.18 /cm.sup.2, a film thickness of the buried oxide film 2 is 800 angstroms. The method of forming by sticking silicon substrates with oxidized surface may also be adopted.
Next, part of the silicon layer 3 is removed by the reactive ion etching (RIE) using photoresist and an active region for formation of elements is formed in the remaining region. The active region may be formed by oxidizing an isolation region by the selective oxidation method. Next, boron of about 5.times.10.sup.11 /cm.sup.2 is implanted at 20 keV to form the channel formation region 4 in the silicon layer 3. Although impurities of p-type are introduced herein, impurities of n-type may possibly be introduced depending on circumstances.
Subsequently, with the gate insulating film 7 of about 100 angstroms interposed therebetween, a gate electrode material formed of an n-type polysilicon film doped with phosphorus is deposited. Now, photoresist (not shown) is provided in a region to be the gate electrode 8 and the polysilicon film is etched using it as a mask to form the gate electrode 8. After removing the photoresist, phosphorus is added to about 1.times.10.sup.13 cm.sup.2 at 30 keV to form the additional drain region 5 and the additional source region 5'. Furthermore, after depositing a CVD oxide film of about 1500 angstroms, the sidewalls 9 are formed on the side wall of the gate electrode 8 by RIE. Next, arsenic is added to about 2.times.10.sup.15 /cm.sup.2 at 50 keV to form the drain region 6 and the source region 6', thus obtaining the structure shown in FIG. 13.
If a low dose substrate with the buried oxide film 2 thinner than about 1000 angstroms is used as an SOI substrate, there were problems as described below. First, if the concentration of the silicon substrate 1 is low, a depletion layer deeply extends in the silicon substrate. The length td of the depletion layer is obtained from the equation (I) below. EQU V=q.multidot.Na.multidot.(t box.multidot.td/.epsilon.ox+td.sup.2 /2 .epsilon. si) (I)
Here, V is an applied voltage applied over the buried oxide film 2, q is an elementary electric charge amount, Na is a substrate concentration, t box is a film thickness of the buried oxide film 2 and .epsilon. ox is a dielectric constant of the silicon oxide film.
In the case of the substrate concentration (concentration of impurity of the substrate) of 1.times.10.sup.15 /cm.sup.3 and the film thickness of the buried oxide film 2 of 800 angstroms, when the applied voltage V is 2.5 V, a width of the depletion layer in the vicinity of the drain reaches 1.8 .mu.m. If the depletion layer extends such long, as shown by the arrow in FIG. 14, potential in the silicon substrate 1 under the channel formation region 4 increases. The increase of the potential in the silicon substrate 1 increases potential in the lower part of the channel formation region 4 itself, causing a problem of being weak to the short channel effect.
FIG. 15 shows the potential distribution of an NMOS with the single drain structure with the channel length (gate length) L=0.5 .mu.m, a film thickness of the silicon layer 3 of 1000 angstroms, a film thickness of the buried oxide film 2 of 800 angstroms, an impurity concentration of the silicon substrate 1 of 1.times.10.sup.14 /cm.sup.3 and an impurity concentration of the channel formation region 4 of 5.times.10.sup.16 /cm.sup.3, which was obtained by device simulation. Here, the gate material is n.sup.+ polysilicon gate, the gate voltage is 0 V, and the drain voltage is 0.1 V. It is well seen from the results of the device simulation that the potential rises in the silicon substrate 1.
In order to suppress the increase of the potential, a method of increasing the substrate concentration of the silicon substrate 1 is possible. For example, if the substrate concentration is set to 1.times.10.sup.18 /cm.sup.3 and the film thickness of the buried oxide film is set to 800 angstroms, the thickness of a depletion layer becomes very small as about 100 angstroms in the case of application of 2.5 V. Accordingly, the increase of the potential under the channel formation region 4 can be suppressed to suppress the short channel effect.
As a result of increasing the substrate concentration of the silicon substrate 1, however, the extension of a depletion layer in the silicon substrate 1 under the drain region 6 is also suppressed, increasing the junction capacitance in this region, and which will produce another problem that the high speed operation, which is a feature of the SOI, is not obtained.
The problems of the conventional semiconductor device of the LDD structure discussed above can be summarized as follows.
*If the concentration of the silicon substrate is low, a depletion layer extends under the channel formation region and potential in that region increases. This will cause an increase in potential in the lower portion of the channel formation region (in the interface with the buried oxide film), increase the leakage current, and deteriorate performance characteristics.
*Increasing the concentration of the silicon substrate to suppress the potential increase to suppress the leakage current will also suppress the extension of a depletion layer under the drain to increase the drain capacitance, and which will reduce the operation speed.